R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 457

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
8.4.3
(1)
In auto request mode, transfer request signals are automatically generated within the EXDMAC in
cases where a transfer request signal is not issued from outside, such as in transfer between two
memories, or between a peripheral module that is not capable of generating transfer requests and
memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
(2)
In external request mode, transfer is started by a transfer request signal (EDREQ) from a device
external to this LSI. DMA transfer is started when EDREQ is input while DMA transfer is enabled
(EDA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level
sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level
sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).
Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance
to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer
processing has been started in response to a single external request. The EDRAK signal enables
the external device to determine the timing of EDREQ signal negation, and makes it possible to
provide handshaking between the transfer request source and the EXDMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output
only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block
unit.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Auto Request Mode
External Request Mode
DMA Transfer Requests
Section 8 EXDMA Controller (EXDMAC)
Page 427 of 1372