R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 569

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
[Legend]
⎯:
• P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
SSU settings
SSUMS
MSS
SCKS
Pin state
SSU settings
SAE1
TPU channel 1
settings
P15DDR
NDER13
Pin function
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits
IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in
TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and
BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1
and SSI0S0 in PFCR5, and bit P15DDR.
Not used as the SSU pin (can be used as an I/O port).
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
3. SSI0-A input when SCS0S1 and SCS0S0 = B'00 in PFCR5. Do not set up for TPU
4. SSI0-A output when SCS0S1 and SCS0S0 = B'00 in PFCR5. Do not set up for TPU or
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC
input when phase counting mode is set for channels 2 and 4.
output or DMAC with SCS0-A input.
DMAC with SCS0-A output.
(1) in table
TIOCB1
output
below
(1)
⎯
⎯
⎯
0
0
SSCK
input
(2)
1
input
P15
⎯
0
(1) in table below
0
(2) in table below
TCLKC input*
0
(1)
⎯
0
output
P15
TIOCB1 input*
1
0
1
output
SSCK
(3)
2
1
output
PO13
1
1
1
(1)
⎯
0
DACK1
output
⎯
⎯
⎯
1
0
SSCK
input
(2)
1
(2) in table
SSI0-A
input*
below
1
0
(1)
Section 10 I/O Ports
⎯
3
0
⎯
⎯
⎯
Page 539 of 1372
(3) in table
1
output*
SSI0-A
below
output
SSCK
⎯
(3)
1
4