HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 14

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.2
Section 8 Data Transfer Controller (DTC) ........................................................103
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Section 9 I/O Ports.............................................................................................127
9.1
Rev. 7.00 Sep. 11, 2009 Page xii of xxxiv
REJ09B0211-0700
Bus Arbitration................................................................................................................... 101
7.2.1
7.2.2
Features .............................................................................................................................. 103
Register Configuration....................................................................................................... 105
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
Activation Sources ............................................................................................................. 109
Location of Register Information and DTC Vector Table ................................................. 110
Operation............................................................................................................................ 114
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
Procedures for Using DTC................................................................................................. 123
8.6.1
8.6.2
Examples of Use of the DTC ............................................................................................. 123
8.7.1
8.7.2
8.7.3
Usage Notes ....................................................................................................................... 126
8.8.1
8.8.2
8.8.3
Port 1.................................................................................................................................. 130
9.1.1
9.1.2
Order of Priority of the Bus Masters..................................................................... 101
Bus Transfer Timing ............................................................................................. 101
DTC Mode Register A (MRA) ............................................................................. 106
DTC Mode Register B (MRB).............................................................................. 107
DTC Source Address Register (SAR)................................................................... 107
DTC Destination Address Register (DAR)........................................................... 107
DTC Transfer Count Register A (CRA) ............................................................... 107
DTC Transfer Count Register B (CRB)................................................................ 108
DTC Enable Registers (DTCER) .......................................................................... 108
DTC Vector Register (DTVECR)......................................................................... 109
Normal Mode........................................................................................................ 115
Repeat Mode ......................................................................................................... 116
Block Transfer Mode ............................................................................................ 117
Chain Transfer ...................................................................................................... 119
Interrupts............................................................................................................... 120
Operation Timing.................................................................................................. 120
Number of DTC Execution States ........................................................................ 121
Activation by Interrupt.......................................................................................... 123
Activation by Software ......................................................................................... 123
Normal Mode........................................................................................................ 123
Chain Transfer ...................................................................................................... 124
Software Activation .............................................................................................. 125
Module Stop Mode Setting ................................................................................... 126
On-Chip RAM ...................................................................................................... 126
DTCE Bit Setting.................................................................................................. 126
Port 1 Data Direction Register (P1DDR).............................................................. 130
Port 1 Data Register (P1DR)................................................................................. 131