HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 61

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
7
6
5
4
3
2
1
Bit Name
I
UI
H
U
N
Z
V
Initial Value
1
undefined
undefined
undefined
undefined
undefined
undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI
is accepted regardless of the I bit setting. The I bit is
set to 1 by hardware at the start of an exception-
handling sequence. For details, refer to section 5,
Interrupt Controller.
User Bit or Interrupt Mask Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit
cannot be used as an interrupt mask bit in this LSI.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this flag is
set to 1 if there is a carry or borrow at bit 3, and
cleared to 0 otherwise. When the ADD.W, SUB.W,
CMP.W, or NEG.W instruction is executed, the H
flag is set to 1 if there is a carry or borrow at bit 11,
and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed,
the H flag is set to 1 if there is a carry or borrow at
bit 27, and cleared to 0 otherwise.
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as
a sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
Rev. 7.00 Sep. 11, 2009 Page 25 of 566
REJ09B0211-0700
Section 2 CPU