HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 439

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit register containing flags that enable or disable
requests by individual interrupt sources. The interrupt flag cannot be masked.
Bit
15
14
13
12
11
10
9
8
Bit Name
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
—
Initial Value
1
1
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Overload Frame
When this bit is cleared to 0, OVR0 (interrupt
request by IRR7) is enabled. When set to 1, OVR0
is masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR6) is enabled. When set to 1, ERS0
is masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR5) is enabled. When set to 1, ERS0
is masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR4) is enabled. When set to 1, OVR0
is masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR3) is enabled. When set to 1, OVR0
is masked.
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR2) is enabled. When set to 1, OVR0
is masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt
request by IRR1) is enabled. When set to 1, RMI is
masked.
Reserved
This bit is always read as 0. Only 0 should be
written to this bit.
Section 15 Controller Area Network (HCAN)
Rev. 7.00 Sep. 11, 2009 Page 403 of 566
REJ09B0211-0700