HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 438

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Controller Area Network (HCAN)
15.3.12 Mailbox Interrupt Mask Register (MBIMR)
The mailbox interrupt mask register (MBIMR) is a 16-bit register that controls the enabling or
disabling of individual mailbox (buffer) interrupt requests.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rev. 7.00 Sep. 11, 2009 Page 402 of 566
REJ09B0211-0700
Bit Name
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
Initial Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or
transmission cancellation. The interrupt source in a
receive mailbox is RXPR setting on reception end.