HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 360

IC H8S MCU FLASH 128K 80QFP

HD64F2612FA20

Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
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Section 14 Serial Communication Interface (SCI)
14.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ between normal serial communication interface mode and Smart Card
interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
Rev. 7.00 Sep. 11, 2009 Page 324 of 566
REJ09B0211-0700
Bit Name
TDRE
RDRF
Serial Status Register (SSR)
Initial Value
1
0
R/W
R/W
R/W
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
[Clearing conditions]
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared to 0.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
data can be written to TDR
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt
request and writes data to TDR
When serial reception ends normally and receive
data is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When the DTC is activated by an RXI interrupt and
transferred data from RDR

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