HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 367

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 14.2 Relationships between the N Setting in BRR and Bit Rate B
Mode
Asynchronous
Mode
Clocked
Synchronous
Mode
Smart Card
Interface Mode
Notes: B: Bit rate (bit/s)
0
0
1
1
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N
settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 14.5 and 14.7
show the maximum bit rates with external clock input.
CKS1
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
Bit Rate Register (BRR)
0
1
0
1
CKS0
Bit Rate
B =
B =
B =
64 × 2
S × 2
8 × 2
2n+1
2n-1
φ × 10
φ × 10
φ × 10
2n-1
0
1
2
3
n
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
Error
Error (%) = {
—
Error (%) = {
Section 14 Serial Communication Interface (SCI)
0
0
1
1
BCP1
Rev. 7.00 Sep. 11, 2009 Page 331 of 566
B × 64 × 2
SMR Setting
B × S × 2
0
1
0
1
BCP0
φ × 10
φ × 10
2n+1
2n-1
6
6
× (N + 1)
× (N + 1)
REJ09B0211-0700
32
64
372
256
S
− 1 } × 100
− 1 } × 100