HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 355

• Manufacturer Part Number: HD64F2612FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2612FA20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 43
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
5
4
3
2
Bit Name
GM
BLK
PE
O/E
BCP1
BCP0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND setting
is advanced by 11.0 etu (Elementary Time Unit: the
time for transfer of 1 bit), and clock output control
mode addition is performed. For details, refer to
section 14.7.8, Clock Output Control.
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 14.7.3, Block Transfer Mode.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data in transmission, and the parity bit is
checked in reception. In Smart Card interface mode,
this bit must be set to 1.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card interface
mode, refer to section 14.7.2, Data Format (Except for
Block Transfer Mode).
Basic Clock Pulse 1 and 2
These bits specify the number of basic clock periods
in a 1-bit transfer interval on the Smart Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin in Smart Card
Interface Mode. S stands for the value of S in BRR
(see section 14.3.9, Bit Rate Register (BRR)).
Section 14 Serial Communication Interface (SCI)
Rev. 7.00 Sep. 11, 2009 Page 319 of 566
REJ09B0211-0700