HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet - Page 376
HD64F2612FA20
Manufacturer Part Number
HD64F2612FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2612FA20
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 14 Serial Communication Interface (SCI)
14.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in figure 14.3. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
Where M : Reception margin
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Rev. 7.00 Sep. 11, 2009 Page 340 of 566
REJ09B0211-0700
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = { (0.5 −
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode
2N
0
1
8 clocks
Start bit
) −
D − 0.5
16 clocks
N
7
− (L − 0.5) F} × 100 [%]
15 0
D0
... Formula (1)
7
15 0
D1
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