DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 181

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 8.4
8.5.3
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size can be between 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt is requested.
Table 8.5 lists the register information in block transfer mode. Figure 8.8 shows the memory
mapping in block transfer mode.
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
SAR
or
DAR
Block Transfer Mode
Register Information in Repeat Mode
Figure 8.7 Memory Mapping in Repeat Mode
Repeat area
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Transfer
Rev. 5.00 Sep. 01, 2009 Page 129 of 656
Section 8 Data Transfer Controller (DTC)
Function
Designates source address
Designates destination address
Holds number of transfers
Designates transfer count
Not used
REJ09B0071-0500
DAR
or
SAR