DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 450

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
Rev. 5.00 Sep. 01, 2009 Page 398 of 656
REJ09B0071-0500
1
Bit
Bit Name
IRIC
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Initial
Value
0
R/W
R/W
Description
I
Also see table 14.4.
[Setting conditions]
In I
•
•
•
•
•
In I
•
•
•
•
With clocked synchronous serial format
•
•
When a condition occurs in which internal flag of TDRE and
RDFR is set to 1 except for the above
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
When ICDR is read/written by DTC (H8S/2268 Group only)
(When TDRE or RDRF flag is cleared to 0)
(As it might not be a condition to clear, for details, see section
14.4.8.
2
C Bus Interface Interrupt Request Flag
2
2
C bus format master mode
C bus format slave mode
When a start condition is detected in the bus line state after
a start condition is issued (when the TDRE flag is set to 1
because of first frame transmission)
When a wait is inserted between the data and acknowledge
bit when WAIT = 1
At the end of data transfer (when the TDRE or RDRF flag is
set to 1)
When a slave address is received after bus arbitration is lost
(when the AL flag is set to1)
When 1 is received as the acknowledge bit when the ACKE
bit is 1 (when the ACKB bit is set to 1)
When the slave address (SVA, SVAX) matches (when the
AAS and AASX flags are set to 1) and at the end of data
transfer up to the subsequent retransmission start condition
or stop condition detection (when the TDRE or RDRF flag is
set to 1)
When the general call address (one frame including a R/W
bit is H'00) is detected (when the ADZ flag is set to 1) and at
the end of data transfer up to the subsequent retransmission
start condition or stop condition detection (when the TDRE
or RDRF flag is set to 1)
When 1 is received as the acknowledge bit when the ACKE
bit is 1 (when the ACKB bit is set to 1)
When a stop condition is detected (when the STOP or ESTP
flag is set to 1)
At the end of data transfer (when the TDRE or RDRF flag is
set to 1)
When a start condition is detected with serial format selected