DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 378

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
13.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 13.2 The Relationships between the N Setting in BRR and Bit Rate B
Note: B: Bit rate (bit/s)
Rev. 5.00 Sep. 01, 2009 Page 326 of 656
REJ09B0071-0500
Communication
Mode
Asynchronous
Mode
Clocked
Synchronous Mode
Smart Card
Interface Mode
CKS1
0
0
1
1
SMR Setting
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
Bit Rate Register (BRR)
CKS0
0
1
0
1
ABCS bit
0
1
⎯
⎯
Clock
Source
φ
φ/4
φ/16
φ/64
Bit Rate
B =
B =
B =
B =
n
0
1
2
3
64 × 2
32 × 2
S × 2
8 × 2
2n+1
φ × 10
φ × 10
φ × 10
2n-1
φ × 10
2n-1
2n-1
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
6
BCP1
0
0
1
1
Error
Error (%) = {
Error (%) = {
⎯
Error (%) = {
SMR Setting
BCP0
0
1
0
1
B × 64 × 2
B × 32 × 2
B × S × 2
φ × 10
φ × 10
φ × 10
2n+1
2n-1
2n-1
S
32
64
372
256
6
6
6
× (N + 1)
× (N + 1)
× (N + 1)
-1 } × 100
-1 } × 100
-1 } × 100