DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 464

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.4.4
In I
and returns an acknowledge signal. The slave device transmits data.
The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame
after a start condition is generated in the master transmit mode. After the slave device is selected
the switch to receive operation takes place.
(1) Receive Operation Using Wait States
Figures 14.10 and 14.11 are flowcharts showing examples of the master receive mode (WAIT =
1).
Rev. 5.00 Sep. 01, 2009 Page 412 of 656
REJ09B0071-0500
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
IRIC
IRTR
ICDR
User processing
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
Figure 14.9 Example of Master Transmit Mode Stop Condition Generation Timing
Master Receive Operation
2
Data 1
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Bit 0
8
Data 1
[7]
[9] ICDR write
9
A
Bit 7
1
Bit 6
(MLS = WAIT = 0)
2
[9] IRIC clearance
Bit 5
3
Data 2
Bit 4 Bit 3
4
Data 2
5
Bit 2
6
Bit 1 Bit 0
7
[11] ACKB read
8
[12] IRIC clearance
[10]
A
9
[12] Write BBSY = 0
Stop condition
generated
and SCP = 0
(stop condition
issued)