HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 128
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 128 of 932
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6. Interrupt Controller (INTC)
6.3.2
ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0
to IRQ7. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the
edge detection mode by the sense select bits of IRQ0 to IRQ 7 in Interrupt control register 1
(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the
setting of ICR2 is ignored.
Rev.4.00 Mar. 27, 2008 Page 82 of 882
REJ09B0108-0400
Bit
15
14
13
12
11
10
Bit Name
IRQ0ES1
IRQ0ES0
IRQ1ES1
IRQ1ES0
IRQ2ES1
IRQ2ES0
Interrupt Control Register 2 (ICR2)
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This bit sets the IRQ0 interrupt request edge
detection mode.
00: Interrupt request is detected on falling edge of
01: Interrupt request is detected on rising edge of
10: Interrupt request is detected on both of falling
11: Cannot be set
This bit sets the IRQ1 interrupt request edge
detection mode.
00: Interrupt request is detected on falling edge of
01: Interrupt request is detected on rising edge of
10: Interrupt request is detected on both of falling
11: Cannot be set
This bit sets the IRQ2 interrupt request edge
detection mode.
00: Interrupt request is detected on falling edge of
01: Interrupt request is detected on rising edge of
10: Interrupt request is detected on both of falling
11: Cannot be set
IRQ0 input
IRQ0 input
and rising edge of IRQ0 input
IRQ1 input
IRQ1 input
and rising edge of IRQ1 input
IRQ2 input
IRQ2 input
and rising edge of IRQ2 input
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