HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 311
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Example of Synchronous Operation Setting Procedure:
Figure 11.11 shows an example of the synchronous operation setting procedure.
Example of Synchronous Operation: Figure 11.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM
cycle.
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to,
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
<Synchronous presetting>
Synchronous presetting
Synchronous operation
operation.
the same value is simultaneously written to the other TCNT counters.
Figure 11.11
Set synchronous
Set TCNT
operation
selection
Example of Synchronous Operation Setting Procedure
[1]
[2]
Synchronous clearing
<Counter clearing>
source generation
clearing source
Select counter
Start count
channel?
Clearing
Yes
11.
Rev.4.00 Mar. 27, 2008 Page 265 of 882
No
[3]
[5]
Multi-Function Timer Pulse Unit (MTU)
<Synchronous clearing>
Set synchronous
counter clearing
Start count
REJ09B0108-0400
[4]
[5]
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