HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 89
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 89 of 932
- Download datasheet (6Mb)
• System Control Instructions
Instruction
CLRT
CLRMAC
LDC
LDC
LDC
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS
LDS
LDS
LDS.L @Rm+,MACH 0100mmmm00000110
LDS.L @Rm+,MACL 0100mmmm00010110
LDS.L @Rm+,PR
NOP
RTE
SETT
SLEEP
STC
STC
STC
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STS
STS
STS
STS.L MACH,@–Rn 0100nnnn00000010
STS.L MACL,@–Rn 0100nnnn00010010
STS.L PR,@–Rn
Rm,SR
Rm,GBR
Rm,VBR
Rm,MACH
Rm,MACL
Rm,PR
SR,Rn
GBR,Rn
VBR,Rn
MACH,Rn
MACL,Rn
PR,Rn
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00100110
0000000000001001
0000000000101011
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00100010
Operation
0 → T
0 → MACH, MACL
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
No operation
Delayed branch, stack area
→ PC/SR
1 → T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
Rn – 4 → Rn, SR → (Rn)
Rn – 4 → Rn, GBR → (Rn)
Rn – 4 → Rn, BR → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn – 4 → Rn, MACH → (Rn)
Rn – 4 → Rn, MACL → (Rn)
Rn – 4 → Rn, PR → (Rn)
Rev.4.00 Mar. 27, 2008 Page 43 of 882
REJ09B0108-0400
Execution
States
1
1
1
1
1
3
3
3
1
1
1
1
1
1
1
4
1
3*
1
1
1
2
2
2
1
1
1
1
1
1
2. CPU
T Bit
0
—
LSB
—
—
LSB
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
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