HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 520
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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14. I
• I
• Synchronous serial format:
14.3.4
ICMR sets the transfer format and transfer rate. ICMR is only accessible when the ICE bit in
ICCR is set to 1.
Rev.4.00 Mar. 27, 2008 Page 474 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
Addressing format with an acknowledge bit
Non-addressing format without an acknowledge bit, and with master operation only
2
C bus format:
2
C Bus Interface (IIC) Option
Bit Name
MLS
WAIT
CKS2
CKS1
CKS0
I
2
C Bus Mode Register (ICMR)
Initial Value
0
0
0
0
0
R/W Description
R/W MSB First/LSB First Select
R/W Wait Insertion
R/W
R/W
R/W
0: MSB first
1: LSB first
When this module is used in the I
should be set to 0.
This bit is enabled only in master mode of the I
format.
0: A wait state is not inserted, and data and the
1: After the clock for the final bit of the data (8th cycle)
For details, refer to section 14.4.7, Timing for Setting
IRIC and the Control of SCL.
Transfer Clock Select 2 to 0
The CKS2 to CKS0 bits, together with the IICX0 bit in
SCRX, select the frequency of the transfer clock. This is
used in the master mode. See table 14.3.
acknowledge bit are transferred consecutively.
become low, the IRIC flag in ICCR is set to 1, and a
wait state is entered (with SCL at the low level).
Clearing the IRIC flag in ICCR to 0 cancels the wait
state. The acknowledge bit is then transferred.
2
C bus format, this bit
2
C bus
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