HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 462
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 462 of 932
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13. Serial Communication Interface (SCI)
13.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and the effective bit rate B
clocked synchronous, and smart card interface modes. The initial value of BRR is H'FF, and it can
be read from or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Effective Bit Rate B
[Legend]
B
B
N:
Pφ:
n and S:
Rev.4.00 Mar. 27, 2008 Page 416 of 882
REJ09B0108-0400
Mode
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Clocked synchronous
mode (n = 1 to 3)
Smaet card interface
mode (n = 0)
Smaet card interface
mode (n = 1 to 3)
0
1
:
:
Effective bit rate (bit/s) Actual transfer speed according to the register settings
Logical bit rate (bit/s) Specified transfer speed of the target system
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Peripheral clock operating frequency (MHz)
Bit Rate Register (BRR)
Determined by the SMR settings shown in the following tables.
Bit Rate
B
B
B
B
B
B
0
0
0
0
0
0
=
=
=
=
=
=
32 × 2
S × 2
S × 2
4 × 2
32 × 2
4 × 2
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
2n+1
2n+1
2n+2
2n+1
2n
2n
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
6
6
6
Error
Error (%) =
Error (%) =
—
—
Error (%) =
Error (%) =
⎞
⎠
⎞
⎠
⎞
⎠
⎞
⎠
B
B
B
B
B
B
B
B
0
for asynchronous,
0
1
0
1
0
1
0
1
– 1 × 100
– 1 × 100
– 1 × 100
– 1 × 100
⎞
⎠
⎞
⎠
⎞
⎠
⎞
⎠
0
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