HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 340

• Manufacturer Part Number: HD64F7145F50
• Description: IC SUPERH MCU FLASH 256K FP144F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7145F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.
6. PWM Cycle Setting
Rev.4.00 Mar. 27, 2008 Page 294 of 882
REJ09B0108-0400
In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in
which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit
value is set. The settings should be made so as to achieve the following relationship between
these two registers:
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3
and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3
and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer
mode register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at
the crest, and from the current cycle when performed in the trough. Figure 11.36 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register Data Updating, for the method of updating the data in each
buffer register.
Multi-Function Timer Pulse Unit (MTU)
Counter value TGRC_3
TGRA_3 set value = TCDR set value + TDDR set value
TGRA_3
update
Figure 11.36
TGRA_3
update
Example of PWM Cycle Updating
TCNT_3
TCNT_4
Time