HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 770
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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24. Power-Down Modes
24.2.2
SYSCR is an 8-bit readable/writable register that performs AUD software reset control and
enables/disables the access to the on-chip RAM.
Bit
7, 6
5 to 2 —
1
0
Rev.4.00 Mar. 27, 2008 Page 724 of 882
REJ09B0108-0400
Bit Name
—
AUDSRST
RAME
System Control Register (SYSCR)
All 1
All 0
Initial Value
0
1
R/W
R
R
R/W
R/W
Description
Reserved
These bits are always read as 1, and should always
be written with 1.
Reserved
These bits are always read as 0, and should always
be written with 0.
AUD Software Reset
This bit controls the AUD reset by software. When 0
is written to AUDSRST, AUD module shifts to power-
on reset state.
0: Shifts to AUD reset state.
1: Clears the AUD reset.
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the
on-chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM
should not be set next to the instruction to write to
SYSCR. If such an instruction is set, normal access
is not guaranteed.
When RAME is set to 1 to enable the on-chip RAM,
an instruction to read SYSCR should be set next to
the instruction to write to SYSCR. If an instruction to
access the on-chip RAM is set next to the instruction
to write to SYSCR, normal access is not guaranteed.
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