DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 195

• Manufacturer Part Number: DF2377RVFQ33
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt Control
Mode
0
2
5.6.1
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
interrupt request is sent to the interrupt controller.
pending. If the I bit is cleared, an interrupt request is accepted.
the priority system is accepted, and other interrupt requests are held pending.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority Setting
Registers
Default
IPR
Interrupt
Mask Bits
I
I2 to I0
Description
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
The priorities of interrupt sources are fixed at
8 priority levels except for NMI can be set with
Rev.7.00 Mar. 18, 2009 page 127 of 1136
Section 5 Interrupt Controller
REJ09B0109-0700