DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 497

• Manufacturer Part Number: DF2377RVFQ33
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.2.2
MRB selects the DTC operating mode.
Bit
7
6
5
4
to
0
9.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
9.2.4
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
CHNS
Bit Name
CHNE
DISEL
—
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
DTC Destination Address Register (DAR)
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
—
—
—
—
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination
of the end of the specified number of transfers,
clearing of the activation source flag, and clearing
of DTCER is not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
Rev.7.00 Mar. 18, 2009 page 429 of 1136
Section 9 Data Transfer Controller (DTC)
REJ09B0109-0700