DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 779

• Manufacturer Part Number: DF2377RVFQ33
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous
Mode
Clocked
Synchronous
Mode
Smart Card
Interface Mode
Note: B: Bit rate (bit/s)
0
0
1
1
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N
settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with
external clock input.
CKS1
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
Bit Rate Register (BRR)
0
1
0
1
CKS0
Bit Rate
B =
B =
B =
64 × 2
S × 2
8 × 2
2n−1
2n+1
φ × 10
φ × 10
φ × 10
2n−1
0
1
2
3
n
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
Section 15 Serial Communication Interface (SCI, IrDA)
Error
Error (%) = {
Error (%) = {
0
0
1
1
BCP1
Rev.7.00 Mar. 18, 2009 page 711 of 1136
B × 64 × 2
B × S × 2
SMR Setting
0
1
0
1
BCP0
φ × 10
φ × 10
2n+1
2n−1
6
6
× (N + 1)
× (N + 1)
REJ09B0109-0700
32
64
372
256
S
− 1 } × 100
− 1 } × 100