DF2377RVFQ33 Renesas Electronics America, DF2377RVFQ33 Datasheet - Page 772

• Manufacturer Part Number: DF2377RVFQ33
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
Bit
5
4
Rev.7.00 Mar. 18, 2009 page 704 of 1136
REJ09B0109-0700
Bit Name
ORER
FER
Initial Value
0
0
R/W
R/(W) *
R/(W) *
Description
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
When 0 is written to ORER after reading ORER
= 1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the FER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
When 0 is written to FER after reading FER = 1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.