AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 106

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

106
AT8xC51SND1C
Reset Value = 0000 0000b
Table 101. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
Reset Value = XXh
Table 102. UBYCTX Register
UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
Number
Number
FDAT7
7 - 3
7 - 0
Bit
Bit
2
1
0
7
7
-
Mnemonic Description
Mnemonic Description
FDAT7:0
EP2INT
EP1INT
EP0INT
BYCT6
FDAT6
Bit
Bit
6
6
-
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 2. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 1 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 1. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 0 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 0. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint X FIFO Data
Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
BYCT5
FDAT5
5
5
FDAT4
BYCT4
4
4
BYCT3
FDAT3
3
3
BYCT2
FDAT2
2
2
BYCT1
FDAT1
1
1
4109L–8051–02/08
BYCT0
FDAT0
0
0