AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 138

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

18.4.0.2
18.4.1
18.4.2
18.4.3
138
AT8xC51SND1C
Transmission (Modes 1, 2
and 3)
Reception (Modes 1, 2 and 3)
Framing Error Detection (Modes 1, 2 and 3)
Modes 2 and 3
Figure 18-9. Data Frame Format (Mode 1)
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 18-10) con-
sists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and
received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On
transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the
ninth bit can be used as a command/data flag.
Figure 18-10. Data Frame Format (Modes 2 and 3)
To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according to
Table 124, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be transmitted to
SBUF register starts the transmission.
To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to
Table 124, and set the REN bit. The actual reception is then initiated by a detected high-to-low
transition on the RXD pin.
Framing error detection is provided for the three asynchronous modes. To enable the framing bit
error detection feature, set SMOD0 bit in PCON register as shown in Figure 18-11.
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
2 devices. If a valid stop bit is not found, the software sets FE bit in SCON register.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the
last data bit as detailed in Figure 18-17.
Figure 18-11. Framing Error Block Diagram
Mode 1
Start bit
Start bit
Framing Error
D0
Controller
D0
D1
D1
D2
FE
D2
SM0
D3
9-bit data
D3
SMOD0
8-bit data
PCON.6
D4
1
0
D4
D5
D5
D6
SM0/FE
SCON.7
D6
D7
D7
D8
Stop bit
4109L–8051–02/08
Stop bit