AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 171

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

Table 141. Status for Slave Transmitter Mode
Table 142. Status for Miscellaneous States
4109L–8051–02/08
SSSTA
SSSTA
Status
Status
Code
Code
A8h
B0h
B8h
C0h
C8h
F8h
00h
Status of the TWI Bus
and TWI Hardware
Own SLA+R has been
received; ACK has
been returned
Arbitration lost in
SLA+R/W as master;
own SLA+R has been
received; ACK has
been returned
Data Byte in SSDAT
has been transmitted;
ACK has been
received
Data Byte in SSDAT
has been transmitted;
NOT ACK has been
received
Last data Byte in
SSDAT has been
transmitted
(SSAA= 0); ACK has
been received
Status of the TWI Bus
and TWI Hardware
No relevant state
information available;
SSI = 0
Bus error due to an
illegal START or STOP
condition
To/From SSDAT
Write data Byte
Write data Byte
Write data Byte
Write data Byte
Write data Byte
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
To/From SSDAT
No SSDAT action
No SSDAT action
Application Software Response
Application Software Response
SSSTA
SSSTA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
No SSCON action
SSSTO
SSSTO
To SSCON
To SSCON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SSI
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
SSAA
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Last data Byte will be transmitted.
Data Byte will be transmitted.
Last data Byte will be transmitted.
Data Byte will be transmitted.
Last data Byte will be transmitted.
Data Byte will be transmitted.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Next Action Taken by TWI Hardware
Wait or proceed current transfer.
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the bus is
released and SSSTO is reset.
AT8xC51SND1C
171