AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 29

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

7.3
7.3.1
4109L–8051–02/08
Dual Data Pointer
Description
in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode,
refer to the Section “X2 Feature”, page 13.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the
M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to
15 CPU clock periods.
For simplicity,
provide precise timing information. For bus cycle timing parameters refer to the Section “AC
Characteristics”.
Figure 4. External Data Read Waveforms
Notes:
Figure 5. External Data Write Waveforms
Notes:
The AT8xC51SND1C implement a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
CPU Clock
1.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
1.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
CPU Clock
RD
puts SFR content instead of DPH.
WR
puts SFR content instead of DPH.
RD
ALE
WR
Figure 4
signal may be stretched using M0 bit in AUXR register.
P0
P2
ALE
signal may be stretched using M0 bit in AUXR register.
(1)
P0
P2
(1)
P2
and
P2
Figure 5
DPL or Ri
DPL or Ri
depict the bus cycle waveforms in idealized form and do not
DPH or P2
DPH or P2
(2),(3)
(2),(3)
D7:0
AT8xC51SND1C
D7:0
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