AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 88

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

15.4.2
88
AT8xC51SND1C
Bulk/Interrupt OUT Transactions in Ping-pong Mode
is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be
read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit
to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0
bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct and the
endpoint Byte counter contains the number of Bytes sent by the Host.
Figure 15-10. Bulk/Interrupt OUT Transactions in Ping-pong Mode
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the correspond-
ing endpoint, store the number of data Bytes by reading the UBYCTX register. If the received
packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has
to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to
allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action
switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,
the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint
FIFO.
When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 end-
OUT
OUT
OUT
HOST
DATA0 (n Bytes)
DATA1 (m Bytes)
DATA0 (p Bytes)
ACK
ACK
ACK
UFI
RXOUTB0
RXOUTB1
RXOUTB0
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte n
Endpoint FIFO bank 1 - Read Byte 1
Endpoint FIFO bank 1 - Read Byte 2
Endpoint FIFO bank 1 - Read Byte m
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte p
Clear RXOUTB0
Clear RXOUTB1
Clear RXOUTB0
C51
4109L–8051–02/08