AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 174

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

21. Analog to Digital Converter
21.1
174
Description
AT8xC51SND1C
The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital converter
(ADC). First channel of this ADC can be used for battery monitoring while the second one can
be used for voice sampling at 8 kHz.
The A/D converter interfaces with the C51 core through four special function registers: ADCON,
the ADC control register (see
150
As shown in Figure 21-1, the ADC is composed of a 10-bit cascaded potentiometric digital to
analog converter, connected to the negative input of a comparator. The output voltage of this
DAC is compared to the analog voltage stored in the Sample and Hold and coming from AIN0 or
AIN1 input depending on the channel selected (see Table 147). The 10-bit ADDAT converted
value (see formula in Figure 21-1) is delivered in ADDH and ADDL registers, ADDH is giving the
8 most significant bits while ADDL is giving the 2 least significant bits. ADDAT
Figure 21-1. ADC Structure
Figure 21-2 shows the timing diagram of a complete conversion. For simplicity, the figure depicts
the waveforms in idealized form and do not provide precise timing information. For ADC charac-
teristics and timing parameters refer to the section “AC Characteristics”.
and
Table
AIN1
AIN0
CLOCK
151); and ADCLK, the ADC clock register (see Table 149).
ADC
ADDAT
ADCON.0
ADCS
0
1
=
1023 V
------------------------- -
Table
ADCON.5
V
Sample and Hold
ADEN
REF
⋅
CONTROL
IN
148); ADDH and ADDL, the ADC data registers (see
AVSS
ADCON.3
ADSST
+
-
AREFP
ADEOC
ADCON.4
R/2R DAC
AREFN
SAR
EADC
IEN1.3
8
2
10
4109L–8051–02/08
ADDH
ADDL
ADC
Interrupt
Request
Table