AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 142

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

18.6.2
18.6.3
18.7
142
Interrupt
AT8xC51SND1C
Broadcast Address
Reset Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don’t-care bits, e.g.:
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most
applications, a broadcast address is FFh.
The following is an example of using broadcast addresses:
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send the address FFh.
To communicate with slaves A and B, but not slave C, the master must send the address FBh.
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb (all don’t care bits). This ensures that the Serial Port is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and
“end of transmission” (TI in SCON) flags. As shown in Figure 18-16 these flags are combined
together to appear as a single interrupt source for the C51 core. Flags must be cleared by soft-
ware when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are glo-
bally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and weather the framing error detection is enabled or dis-
abled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 18-17.
Slave A:SADDR = 1111 0001b
Slave B:SADDR = 1111 0011b
Slave C:SADDR = 1111 0010b
SADDR = 0101 0110b
SADEN = 1111 1100b
(SADDR | SADEN)=1111 111Xb
SADEN = 1111 1010b
Given = 1111 1X11b,
SADEN = 1111 1001b
Given = 1111 1X11b,
SADEN = 1111 1101b
Given = 1111 1111b,
4109L–8051–02/08