AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 84

IC MCU FLASH MP3 DECODER 80-TQFP

AT80C51SND1C-ROTIL

Manufacturer Part Number
AT80C51SND1C-ROTIL
Description
IC MCU FLASH MP3 DECODER 80-TQFP
Manufacturer
Atmel
Series
80Cr
Datasheet

Specifications of AT80C51SND1C-ROTIL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Type
ROMless
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
AT80C51SND1CROTIL

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT80C51SND1C-ROTIL
Manufacturer:
Atmel
Quantity:
10 000
Figure 15-5. UFI Block Diagram
Figure 15-6. USB Typical Transaction Load
15.2
15.2.1
84
Configuration
AT8xC51SND1C
IN Transactions:
OUT Transactions:
General Configuration
HOST
HOST
12 MHz DPLL
To/From SIE
C51
UFI
C51
UFI
OUT
IN
NACK
DATA0 (n Bytes)
Endpoint FIFO Write
USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 19).
The USB controller should be then enabled by setting the EUSB bit in the USBCON register.
Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address should be stored in the USBADDR
register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow
the USB controller to answer only to requests sent at the new address.
Endpoint Control
USB side
Transfer
Control
FSM
ACK
IN
C51 interrupt
Asynchronous Information
Endpoint FIFO read (n Bytes)
DATA1
Endpoint 2
Endpoint 1
Endpoint 0
OUT
DATA1
IN
Endpoint Control
UEPCONX
USBADDR
UEPSTAX
UEPDATX
NACK
UEPNUM
UFNUMH
C51 side
USBCON
UEPRST
UBYCTX
UFNUML
USBIEN
UEPIEN
USBINT
UEPINT
DATA1
OUT
ACK
To/From C51 Core
C51 interrupt
DATA1
Endpoint FIFO write
ACK
4109L–8051–02/08

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