AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 48

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

10. Power Management
10.1
10.1.1
48
Reset
AT8xC51SND1C
Cold Reset
2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and the
Power-down mode. These modes are detailed in the following sections. In addition to these
power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2
using the X2 mode detailed in section “X2 Feature”, page 13.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high
level has to be applied on the RST pin. A bad level leads to a wrong initialization of the internal
registers like SFRs, Program Counter… and to unpredictable behavior of the microcontroller. A
proper device reset initializes the AT8xC51SND1C and vectors the CPU to address 0000h. RST
input has a pull-down resistor allowing power-on reset by simply connecting an external capaci-
tor to V
indirectly by an internal reset source such as the watchdog timer. Resistor value and input char-
acteristics are discussed in the Section “DC Characteristics” of the AT8xC51SND1C datasheet.
The status of the Port pins during reset is detailed in
Figure 10-1. Reset Circuitry and Power-On Reset
Table 58. Pin Conditions in Special Operating Modes
Note:
2 conditions are required before enabling a CPU start-up:
•
•
If one of these 2 conditions are not met, the microcontroller does not start correctly and can exe-
cute an instruction fetch from anywhere in the program space. An active level applied on the
RST pin must be maintained till both of the above conditions are met. A reset is active when the
level V
oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset
pulse width:
•
•
V
The level on X1 input pin must be outside the specification (V
V
Oscillator startup time.
DD
DD
IH1
DD
1. Refer to section “Audio Output Interface”, page 74.
RST
must reach the specified V
rise time,
Reset
Idle
Power-down
as shown in Figure 10-1. A warm reset can be applied either directly on the RST pin or
is reached and when the pulse width covers the period of time where V
Mode
RST input circuitry
VDD
VSS
P
Floating
Port 0
Data
Data
Port 1
DD
High
Data
Data
range
Port 2
Data
Data
High
From Internal
Reset Source
To CPU Core
and Peripherals
Table
Port 3
High
Data
Data
58.
Port 4
High
Data
Data
IH
, V
IL
Power-on Reset
Port 5
)
Data
Data
High
VDD
+
Floating
MMC
Data
Data
RST
4109L–8051–02/08
DD
and the
Audio
Data
Data
1