AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 200

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
• DBW: Data Bus Width
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge
of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• TDF_MODE: TDF Optimization
1: TDF optimization is enabled.
0: TDF optimization is disabled.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
6062M–ATARM–23-Mar-09
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
• 1: Byte write access type:
• 0: Byte select access type:
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
– The number of TDF wait states is optimized using the setup period of the next read/write access.
– The number of TDF wait states is inserted before the next access begins.
0
0
1
1
0
0
1
1
DBW
PS
0
1
0
1
0
1
0
1
Data Bus Width
8-bit bus
16-bit bus
32-bit bus
Reserved
Page Size
4-byte page
8-byte page
16-byte page
32-byte page
AT91SAM9261 Preliminary
200