AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 282
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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27.7.2
27.7.2.1
27.7.2.2
282
AT91SAM9261 Preliminary
Interrupt Latencies
External Interrupt Edge Triggered Source
External Interrupt Level Sensitive Source
Global interrupt latencies depend on several parameters, including:
This section addresses only the hardware resynchronizations. It gives details of the latency
times between the event on an external interrupt leading in a valid interrupt (edge or level) or the
assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro-
cessor. The resynchronization time depends on the programming of the interrupt source and on
its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
Figure 27-6.
Figure 27-7.
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
External Interrupt Edge Triggered Source
External Interrupt Level Sensitive Source
(Negative Edge)
(Positive Edge)
IRQ or FIQ
IRQ or FIQ
nIRQ
MCK
nFIQ
(High Level)
(Low Level)
IRQ or FIQ
IRQ or FIQ
nIRQ
MCK
nFIQ
Maximum IRQ Latency = 4 Cycles
Maximum FIQ Latency = 4 Cycles
Latency = 3 Cycles
Latency = 3 cycles
Maximum IRQ
Maximum FIQ
6062M–ATARM–23-Mar-09
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