AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 203
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AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
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Part Number
Manufacturer
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Price
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22.3.1.2
Table 22-5.
Table 22-6.
Table 22-7.
Notes:
22.4
22.4.1
6062M–ATARM–23-Mar-09
27
27
27
26
26
26
Bk[1:0]
1. M0 is the byte address inside a 16-bit half-word.
4. Bk[1] = BA1, Bk[0] = BA0.
Product Dependencies
25
25
25
SDRAM Device Initialization
Bk[1:0]
Bk[1:0]
16-bit Memory Data Bus Width
24
24
24
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
Bk[1:0]
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
21
21
21
Bk[1:0]
1. SDRAM features must be set in the configuration register: asynchronous timings (TRC,
2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength
3. The SDRAM memory type must be set in the Memory Device Register.
4. A minimum pause of 200 µs is provided to precede any signal toggle.
5.
20
20
20
TRAS, etc.), number of columns, rows, CAS latency, and the data bus width.
(DS) and partial array self refresh (PASR) must be set in the Low Power Register.
(1)
1 in the Mode Register and perform a write access to any SDRAM address.
A NOP command is issued to the SDRAM devices. The application must set Mode to
19
19
19
Row[12:0]
Row[11:0]
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
Row[11:0]
16
16
16
Row[10:0]
Row[12:0]
Row[11:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
Row[10:0]
14
14
14
13
13
13
12
12
12
AT91SAM9261 Preliminary
11
11
11
10
10
10
9
9
9
8
8
8
7
7
7
Column[10:0]
Column[10:0]
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
6
6
6
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
203
0
0
0
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