AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 64

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.5.5.3
12.5.6
64
AT91SAM9261 Preliminary
IEEE 1149.1 JTAG Boundary Scan
Application Board Restriction
Figure 12-5. Half-rate Clocking Mode
Care must be taken on the choice of the trace capture system as it needs to support half-rate
clock functionality.
The TCLK signal needs to be set with care, some timing parameters are required.
The specified target system connector is the AMP Mictor connector.
The connector must be oriented on the application board as shown in
the PCB is shown from above with the trace connector mounted near the edge of the board. This
allows the Trace Port Analyzer to minimize the physical intrusiveness of the interconnected
target.
Figure 12-6. AMP Mictor Connector Orientation
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
ARM926EJ-S Clock
Trace Clock
TraceData
38 37
2
1
AT91SAM9261-based
Application Board
Pin 1Chamfer
Half-rate Clocking Mode
Figure
6062M–ATARM–23-Mar-09
12-6. The view of