AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 305
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Part Number
Manufacturer
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Price
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28.4.2.3
28.4.2.4
28.4.2.5
6062M–ATARM–23-Mar-09
Receiver Ready
Receiver Overrun
Parity Error
Figure 28-4. Start Bit Detection
Figure 28-5. Character Reception
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta-
tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
Figure 28-6. Receiver Ready
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset Status) at 1.
Figure 28-7. Receiver Overrun
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in DBGU_MR. It then compares the result with the received parity
Example: 8-bit, parity enabled 1 stop
Sampling
RXRDY
Sampling Clock
RXRDY
OVRE
DRXD
DRXD
DRXD
Baud Rate
DRXD
Clock
S
S
0.5 bit
period
D0
D0
True Start Detection
D1
D1
period
D2
1 bit
D2
D3
D0
D3
D4
D4
D1
D5
D5
D6
D6
True Start
Detection
D2
D7
D7
P
P
AT91SAM9261 Preliminary
D3
stop
S
S
D4
Read DBGU_RHR
D0
D0
D1
D1
D5
D2
D2
D3
D3
D6
D4
D4
D5
D5
D7
D6
D6
Parity Bit
D7
D7
P
P
stop
Stop Bit
D0
RSTSTA
305
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