AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 238
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 238 of 749
- Download datasheet (12Mb)
24.4.1
24.4.2
6062M–ATARM–23-Mar-09
PLL Filter
Divider and Phase Lock Loop Programming
Figure 24-4. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRCA and/or PLL-
RCB pin.
Figure 24-5. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
MAINCK
Figure 24-5
SLCK
shows a schematic of these filters.
C2
C1
R
Divider B
Divider A
DIVB
DIVA
PLLRC
GND
AT91SAM9261 Preliminary
PLLRCA
PLLRCB
MULB
MULA
PLLBCOUNT
PLLACOUNT
PLL
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
LOCKB
LOCKA
PLLBCK
PLLACK
238
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