MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 180

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Enhanced Capture Timer (ECT) Module
MCEN — Modulus Down-Counter Enable Bit
MCPR1 and MCPR0 — Modulus Counter Prescaler Select Bits
13.4.15 16-Bit Modulus Down-Counter Flag Register
Read: Anytime
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
POLF3–POLF0 — First Input Capture Polarity Status Bits
180
When MCEN = 0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the
modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter prescaler. The newly selected prescaler
division rate will not be effective until a load of the load register into the modulus counter count register
occurs.
The flag is set when the modulus down-counter reaches $0000. Writing 1 to this bit clears the flag.
Writing 0 has no effect. Any access to the MCCNT register will clear the MCZF flag in this register when
TFFCA bit in register TSCR ($86) is set.
This are read-only bits. Writing to these bits has no effect. Each status bit gives the polarity of the first
edge which has caused an input capture to occur after capture latch has been read. Each POLFx
corresponds to a timer PORTx input.
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
Address: $00A7
Reset:
Figure 13-36. 16-Bit Modulus Down-Counter Flag Register (MCFLG)
Read:
Write:
MCZF
Bit 7
0
MCPR1
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
0
0
1
1
5
0
0
MCPR0
0
1
0
1
4
0
0
Division Rate
POLF3
Prescalar
3
0
16
1
4
8
POLF2
2
0
POLF1
1
0
Freescale Semiconductor
POLF0
Bit 0
0