MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 219

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.7.1.2 Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the BDRxD signal transitions, there is a delay before that transition appears at the filtered
Rx data output signal. This delay is between 15 and 16 clock periods, depending on where the transition
occurs with respect to the sampling points. This filter delay must be taken into account when performing
message arbitration.
For example, if the frequency of the MUX interface clock (f
is 954 ns and the maximum filter delay in the absence of noise is 15.259 µs.
The effect of random noise on the BDRxD signal depends on the characteristics of the noise itself. Narrow
noise pulses on the BDRxD signal is ignored completely if they are shorter than the filter delay. This
provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition can be delayed by an amount
equal to the length of the noise burst. This is a reflection of the uncertainty of where the transition is
actually occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length,
are detected by the next stage of the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length are detected normally as an invalid
symbol or as invalid data when the frame’s CRC is checked.
15.7.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the format shown in
J1850 states that each message has a maximum length of 101 PWM bit times or 12 VPW bytes, excluding
SOF, EOD, NB, and EOF, with each byte transmitted most significant bit (MSB) first.
All VPW symbol lengths in the following descriptions are typical values at a 10.4-Kbps bit rate.
15.7.2.1 SOF — Start-of-Frame Symbol
All messages transmitted onto the J1850 bus must begin with a long-active 200 µs period SOF symbol.
This indicates the start of a new message transmission. The SOF symbol is not used in the CRC
calculation.
Freescale Semiconductor
IDLE
SOF
PRIORITY
(Data0)
DATA
Figure 15-4. J1850 Bus Message Format (VPW)
MESSAGE ID
(DATA1)
M68HC12B Family Data Sheet, Rev. 9.1
DATA
n
CRC
BDLC
) is 1.0486 MHz, then the period (t
E
O
D
N
B
OPTIONAL
IFR
Figure
BDLC MUX Interface
EOF
15-4.
F
S
I
BDLC
IDLE
219
)