MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 287

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Read: Anytime
Write: Has no meaning or effect
ADRxH[15:8]–ADRxH[7:0] — ATD Conversion Result Bits
17.4 ATD Mode Operation
Stop
Wait
BDM
User
ADPU
17.5 Using the ATD to Measure a Potentiometer Signal
This exercise allows the student to utilize the ATD on the HC12 to measure a potentiometer signal output
routed from the UDLP1 board to the HC12 ATD pin PAD6. First the ATDCTL registers are initialized. A
delay loop of 100 µs is then executed. The resolution is set up followed by a conversion set up on channel
6. After waiting for the status bit to set, the result goes to the D accumulator. If the program is working
properly, a different value should be found in the D accumulator as the left potentiometer is varied for each
execution of the program.
17.5.1 Equipment
For this exercise, use the M68HC912B32EVB emulation board.
17.5.2 Code Listing
Freescale Semiconductor
The reset condition for these registers is undefined.
These bits contain the left-justified, unsigned result from the ATD conversion. The channel from which
this result was obtained is dependant on the conversion mode selected. These registers are always
read-only in normal mode.
Causes all clocks to halt (if the S bit in the CCR is 0). The system is placed in a minimum-power
standby mode. This aborts any conversion sequence in progress. During STOP recovery, the ATD
must delay for the STOP recovery time (t
ATD conversion continues unless the AWAI bit in ATDCTL2 register is set.
Debug options available as set in register ATDCTL3.
ATD continues running unless ADPU is cleared.
ATD operations are stopped if ADPU = 0, but registers are accessible.
A comment line is deliminted by a semi-colon. If there is no code before
comment, an “;” must be placed in the first column to avoid assembly
errors.
M68HC12B Family Data Sheet, Rev. 9.1
SR
) before initiating a new ATD conversion sequence.
NOTE
ATD Mode Operation
287