MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 222

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MC68HC912B32CFU8

Manufacturer Part Number
MC68HC912B32CFU8
Description
IC MCU 32K FLASH 8MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC68HC912B32CFU8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
768 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Part Number:
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Byte Data Link Communications (BDLC)
15.7.3.1 Logic 0
A logic 0 is defined as:
See
15.7.3.2 Logic 1
A logic 1 is defined as:
See
15.7.3.3 Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is used only in IFR message responses.
15.7.3.4 Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least 240
µs (see
222
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure
Figure
An active-to-passive transition followed by a passive period 64 µs in length, or
A passive-to-active transition followed by an active period 128 µs in length
An active-to-passive transition followed by a passive period 128 µs in length, or
A passive-to-active transition followed by an active period 64 µs in length
Figure
15-5(A).
15-5(B).
15-5(C)).
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 15-5. J1850 VPW Symbols with Nominal Symbol Times
(F) END OF FRAME
(C) BREAK
≥ 240 µs
280 µs
M68HC12B Family Data Sheet, Rev. 9.1
(G) INTER-FRAME
SEPARATION
128 µs
128 µs
20 µs
300 µs
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 µs
OR
OR
IDLE > 300 µs
(H) IDLE
64 µs
64 µs
Freescale Semiconductor
(E) END OF DATA
200 µs

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