MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 295

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The external host should wait 150 E-clock cycles for a non-intrusive BDM command to execute before
another command is sent. This delay includes 128 E-clock cycles for the maximum delay for a free cycle.
For data read commands, the host must insert this delay between sending the address and attempting to
read the data. In the case of a write command, the host must delay after the data portion, before sending
a new command, to be sure the write has finished.
The external host should delay about 32 target E-clock cycles between a firmware read command and
the data portion of these commands. This allows the BDM firmware to execute the instructions needed to
get the requested data into the BDM shifter register.
The external host should delay about 32 target E-clock cycles after the data portion of firmware write
commands to allow BDM firmware to complete the requested write operation before a new serial
command disturbs the BDM shifter register.
The external host should delay about 64 target E-clock cycles after a TRACE1 or GO command before
starting any new serial command. This delay is needed because the BDM shifter register is used as a
temporary data holding register during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU12 operation. However, if an operation
requires multiple cycles, CPU12 clocks are frozen until the operation is complete.
18.3.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active.
Mapping is shown in
The content of the instruction register is determined by the type of background command being executed.
The status register indicates BDM operating conditions. The shift register contains data being received or
transmitted via the serial interface. The address register is temporary storage for BDM commands. The
CCR holding register preserves the content of the CPU12 condition code register while BDM is active.
The only registers of interest to users are the status register and the CCR holding register. The other BDM
registers are used only by the BDM firmware to execute commands. The registers are accessed by
means of the hardware READ_BD and WRITE_BD commands, but should not be written during BDM
operation (except the CCRSAV register which could be written to modify the CCR value).
The instruction register is written by the BDM hardware as a result of serial data shifted in on the BKGD
pin. It is readable and writable in special peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a firmware command is executed.
The instruction register can be read or written in all modes. The hardware clears the instruction register
if 512 E-clock cycles occur between falling edges from the host.
Freescale Semiconductor
$FF02–$FF03
$FF04–$FF05
Address
$FF00
$FF01
$FF06
Table
18-4.
M68HC12B Family Data Sheet, Rev. 9.1
BDM instruction register
BDM status register
BDM shift register
BDM address register
BDM CCR holding register
Table 18-4. BDM Registers
Register
INSTRUCTION
Background Debug Mode (BDM)
Mnemonic
ADDRESS
SHIFTER
CCRSAV
STATUS
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