MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 261

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.11.4 Data Segment Registers
The eight data segment registers (DSR0–DSR7) contain the data to be transmitted or being received. The
number of bytes to be transmitted or received is determined by the data length code in the corresponding
DLR. Data is transmitted starting from the data segment register 0 (DSR0), beginning with the most
significant bit (DB7), and continuing until the number of bytes specified in the data length register (DLR)
is complete.
16.11.5 Transmit Buffer Priority Register
Freescale Semiconductor
Note 1.: x is 4, 5, 6, or 7 depending on which buffer, RxFG, Tx0, Tx1, or Tx3, respectively.
Addr.
$01x4
$01x5
$01x6
$01x7
$01x8
$01x9
$01xA
$01xB
(1)
Data Segment Register 0 (DSR0)
Data Segment Register 1 (DSR1)
Data Segment Register 2 (DSR2)
Data Segment Register 3 (DSR3)
Data Segment Register 4 (DSR4)
Data Segment Register 5 (DSR5)
Data Segment Register 6 (DSR6)
Data Segment Register 7 (DSR7)
Register Name
Address:
Reset:
Read:
Write:
Note 1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2, respectively.
Figure 16-15. Transmit Buffer Priority Register (TBPR)
$01xD
PRIO7
Bit 7
Figure 16-14. Data Segment Registers (DSRn)
PRIO6
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
6
M68HC12B Family Data Sheet, Rev. 9.1
Bit 7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
PRIO5
5
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
6
PRIO4
Unaffected by reset
4
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB5
5
PRIO3
3
Undefined out of reset
Undefined out of reset
Undefined out of reset
Undefined out of reset
Undefined out of reset
Undefined out of reset
Undefined out of reset
Undefined out of reset
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB4
4
Programmer’s Model of Message Storage
PRIO2
2
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
3
PRIO1
1
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DB2
2
PRIO0
Bit 0
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
1
Bit 0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
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