MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 289

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 18
Development Support
18.1 Introduction
Development support involves complex interactions between MCU resources and external development
systems. This section concerns instruction queue and queue tracking signals, background debug mode,
breakpoints, and instruction tagging.
18.2 Instruction Queue
It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.The CPU12 instruction
queue provides at least three bytes of program information to the CPU when instruction execution begins.
The CPU12 always completely finishes executing an instruction before beginning to execute the next
instruction. Status signals IPIPE1 and IPIPE0 provide information about data movement in the queue and
indicate when the CPU begins to execute instructions. Information available on the IPIPE1 and IPIPE0
pins is time multiplexed. External circuitry can latch data movement information on rising edges of the
E-clock signal; execution start information can be latched on falling edges.
of data on the pins.
Freescale Semiconductor
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
IPIPE[1:0]
IPIPE[1:0]
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
M68HC12B Family Data Sheet, Rev. 9.1
Mnemonic
Mnemonic
Table 18-1. IPIPE Decoding
SOD
ALD
SEV
LAT
ALL
INT
—
—
No movement
Latch data from bus
Advance queue and load from bus
Advance queue and load from latch
No start
Start interrupt sequence
Start even instruction
Start odd instruction
Meaning
Meaning
Table 18-1
(1)
(2)
shows the meaning
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