MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 292

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Development Support
Figure 18-3
shows the host receiving a logic 0 from the target MCU. Since the host is asynchronous to
the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start
of the bit time as perceived by the target MCU. The host initiates the bit time but the target MCU finishes
it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 E-clock cycles,
then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after
starting the bit time.
E CLOCK
TARGET MCU
HOST
DRIVE TO
HIGH IMPEDANCE
BKGD PIN
SPEEDUP PULSE
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
Figure 18-3. BDM Target to Host Serial Bit Timing (Logic 0)
18.3.2 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before firmware commands can be
executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single-wire
interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to map
BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background mode.
After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by the
BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firmware
has been enabled causes the MCU to resume normal instruction execution after a brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND
command, but tags activate BDM before a tagged instruction is executed.
In special single-chip mode, background operation is enabled and active immediately out of reset. This
active case replaces the M68HC11 boot function and allows programming a system with blank memory.
While BDM is active, a set of BDM control registers is mapped to addresses $FF00 to $FF06. The BDM
control logic uses these registers which can be read anytime by BDM logic, not user programs. Refer to
18.3.4 BDM Registers
for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function during
BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once normal
program flow is continued, the timer counter is re-enabled to simulate real-time operations.
M68HC12B Family Data Sheet, Rev. 9.1
292
Freescale Semiconductor