MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 207

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.3.5.4 SPI Status Register
Read: Anytime
Write: Has no meaning or effect
SPIF — SPI Interrupt Request Bit
WCOL — Write Collision Status Flag
MODF — SPI Mode Error Interrupt Status Flag
14.3.5.5 SPI Data Register
Read: Anytime; normally, only after SPIF flag set
Write: Anytime; see WCOL write collision flag in
This 8-bit register is both the input and output register for SPI data. Reads of this register are double
buffered but writes cause data to bewritten directly into the serial shifter. In the SPI system, the 8-bit data
register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO wires to
Freescale Semiconductor
SPIF is set after the eighth SCK cycle in a data transfer, and it is cleared by reading the SP0SR register
(with SPIF set) followed by an access (read or write) to the SPI data register.
The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated
because the error status flag can be read upon completion of the transfer that was in progress at the
time of the error. This bit is cleared automatically by a read of the SP0SR (with WCOL set) followed by
an access (read or write) to the SP0DR register.
This bit is set automatically by SPI hardware, if the MSTR control bit is set and the slave select input
pin becomes 0. This condition is not permitted in normal operation. In the case where DDRS bit 7 is
set, the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the
SS input for the SPI system. In this special case, the mode fault function is inhibited and MODF
remains cleared. This flag is cleared automatically by a read of the SP0SR (with MODF set) followed
by a write to the SP0CR1 register.
0 = No write collision
1 = Indicates that a serial transfer was in progress when the MCU tried to write new data into the
SP0DR data register
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
$00D3
$00D5
SPIF
Bit 7
Bit 7
Bit 7
0
Figure 14-18. SPI Status Register (SP0SR)
Figure 14-19. SPI Data Register (SP0DR)
= Unimplemented
WCOL
Bit 6
M68HC12B Family Data Sheet, Rev. 9.1
6
0
6
Bit 5
5
0
0
5
14.3.5.4 SPI Status Register
MODF
Unaffected by reset
Bit 4
4
0
4
Bit 3
3
0
0
3
Bit 2
2
0
0
2
Serial Peripheral Interface (SPI)
Bit 1
1
0
0
1
Bit 0
Bit 0
Bit 0
0
0
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