MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 35

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinout and Signal Descriptions
1.6.4.7 Port P
The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function
is enabled with the PWM enable register (PWEN). Enabling PWM pins takes precedence over the
general-purpose port. When pulse-width modulation is not in use, the port pins may be used for
general-purpose I/O.
The port P data direction register (DDRP) determines pin direction of port P when used for
general-purpose I/O. When DDRP bits are set, the corresponding pin is configured for output. On reset,
the DDRP bits are cleared and the corresponding pin is configured for input.
When the PUPP bit in the PWM control register (PWCTL) register is set, all input pins are pulled up
internally by an active pullup device. Pullups are disabled after reset.
Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels.
Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after
reset. Refer to
Chapter 11 Pulse-Width Modulator
(PWM).
1.6.4.8 Port T
This port provides eight general-purpose I/O pins when not enabled for input capture and output compare
in the timer and pulse accumulator subsystem. The TEN bit in the timer system control register (TSCR)
enables the timer function. The pulse accumulator subsystem is enabled with the PAEN bit in the pulse
accumulator control register (PACTL).
The port T data direction register (DDRT) determines pin direction of port T when used for
general-purpose I/O. When DDRT bits are set, the corresponding pin is configured for output. On reset
the DDRT bits are cleared and the corresponding pin is configured for input.
When the PUPT bit in the timer mask register 2 (TMSK2) is set, all input pins are pulled up internally by
an active pullup device. Pullups are disabled after reset.
Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels.
Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after
reset. For the MC68HC912B32 and MC68HC(9)12BC32, refer to
Chapter 12 Standard Timer
(TIM). For
the MC68HC12BE32, refer to
Chapter 13 Enhanced Capture Timer (ECT)
Module.
1.6.4.9 Port S
Port S is the 8-bit interface to the standard serial interface consisting of the serial communications
interface (SCI) and serial peripheral interface (SPI) subsystems. Port S pins are available for
general-purpose parallel I/O when standard serial functions are not enabled.
Port S pins serve several functions depending on the various internal control registers. If WOMS bit in the
SCI control register 1 (SC0CR1) is set, the P-channel drivers of the output buffers are disabled for bits
0–1 (2–3). If SWOM bit in the SP0CR1 register is set, the P-channel drivers of the output buffers are
disabled for bits 4–7 (wired-OR mode). The open drain control affects both the serial and the
general-purpose outputs. If the RDPSx bits in the PURDS register are set, the appropriate port S pin drive
capabilities are reduced. If PUPSx bits in the port S pullup, reduced drive register (PURDS) are set, the
appropriate pullup device is connected to each port S pin which is programmed as a general-purpose
input. If the pin is programmed as a general-purpose output, the pullup is disconnected from the pin
regardless of the state of the individual PUPSx bits.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
35